1. Field of the Invention
The present invention relates to a small amplitude signal output circuit and, more particularly, to a small amplitude signal output circuit transmitting logic signals between integrated circuits by way of a transmission line.
2. Description of the Related Art
Some output circuits are used as signal transmission means for transmitting signals between two or more integrated circuits via transmission paths such as bus lines. When a logic signal is to be transmitted from an output circuit, the logic signal assumes either H-level or L-level of logical value. Accordingly, there essentially exist in an output circuit of an integrated circuit, an input terminal for receiving internal logic signals from the internal circuit of the integrated circuit, and an output terminal for delivering the internal logic signals to another integrated circuit.
Although most conventional transmission signals have an amplitude close to the power source potential supplied to tie integrated circuit, the signal amplitude has been reduced for transmission in recent years. For instance, in case of a CMOS interface for a conventional transmission signal, the signal amplitude was substantially equal to the power source potential such as about 5V or about 3V. On the other hand, the recent transmission signal having a small amplitude, such as used in a low voltage differential signaling (LVDS) interface, the signal amplitude is as low as about 0.3V. The reason for reduction of the signal amplitude is that the reduction achieves great advantages in higher transmission speed, lower power dissipation, and smaller noise during signal transmission. Accordingly, it is requested that integrated circuits for achieving a higher speed and/or lower power dissipation as the primary objects thereof have an output circuit capable of outputting lower amplitude signals. As a means for outputting the low amplitude signals, some proposals have been offered, and the following is an example thereof.
With reference to FIG. 1 showing a circuit diagram of Pseudo Emitter Coupled Logic interface (PECL interface) as a first conventional output circuit, which is a typical example of a low amplitude interface, the output circuit comprises: a PMOS transistor M11 having a source connected to source line VDD of positive potential, a drain connected to output terminal OUT1 which outputs a low amplitude signal and a gate connected to input terminal IN1; an NMOS transistor M12 having a drain connected to the drain of transistor M11, a gate connected to the gate of transistor M11, and a source connected to source line VSS of ground potential; and a terminal resistor RTT1, having a first terminal connected to output terminal OUT1 and a second terminal connected to a terminal power source VTT.
In general, positive potential is supplied from outside the integrated circuit to source line VDD and source line VSS is grounded. In other cases, source line VDD is grounded, and a negative potential is supplied to source line VSS.
The values of terminal resistor RTT1 and terminal power source potential VTT are generally specified in a standard wherein the former is about 50.OMEGA., and the latter is obtained by subtracting about 2V from the power source potential VDD.
In operation, when a potential at H-level which is close to potential VDD of source line VDD is supplied to input terminal IN1, transistor M11 is OFF and transistor M12 is ON. Thus, a current path is formed from terminal power source VTT to source line VSS via terminal resistor RTT1 and transistor M12. L-level potential VOL of output terminal OUT1 at this stage is expressed by: EQU VOL=VTT-{(VTT-VSS).times.RTT}/(RTT+RONN) (1),
wherein VTT, VSS, RTT and RONN represent potential of power source VTT, potential of source line VSS, resistance of resistor RTT1 and ON-resistance of NMOS transistor M12, respectively.
When potential at L-level which is close to potential VSS of source line VSS is supplied to input terminal IN, transistor M11 is ON and transistor M12 is OFF. Thus a current path is formed from source line VDD to terminal source VTT via transistor M11 and terminal resistor RTT1. Potential VOH at H-level of output terminal OUT1 at this stage is expressed by: EQU VOH=VTT+{(VDD-VTT).times.RTT}/(RTT+RONP) (2),
wherein RONP represents ON-resistance of PMOS transistor M11.
To calculate practical values for H-level VOH and L-level VOL of output OUT1 and relative output signal amplitude (VOH-VOL), each variable in expressions, or formulas, (1) and (2) is set as follows: VDD=3V, VSS=0V, VTT=1.5V, RTT=50.OMEGA., RONN=200.OMEGA., RONP=200 .OMEGA..
After the above values are substituted for the variables in expressions (1) and (2), H-level VOH and L-level VOL of output OUT are calculated as follows: EQU VOH=1.8V (3) EQU VOL=1.2V (4).
Thus, the output signal amplitude is calculated as follows: EQU VOH-VOL=0.6V (5)
The conventional output circuit has a feature that it enables to obtain a desired small signal amplitude by selecting ON-resistances RONP and RONN, which are adjusted based on the size of the transistor elements in the integrated circuit, depending on the power source potentials VDD, VSS, VTT, and terminal resistor RTT which are specified in advance.
Since the first conventional output circuit has a singe output terminal for transmission of a single signal it is generally called a single phase transmission system.
As another transmission system having a low signal amplitude interface, so-called differential transmission system is also used which outputs a pair of transmission signals from respective output terminals. The pair of transmission signals in the differential transmission system have a feature that the phase of the pair of signals are reversed from each other and have equal potentials of H-level and L-level. The reversed phase scheme in the differential transmission system provides twice the dynamic range compared to the single phase transmission system. In addition, there is an advantage that the influence by noise in the power source potential and interference by electromagnetic induction are reduced. In view of this advantage, the differential transmission system is used for a high-speed and high-reliability transmission. Some proposals have been made for the output circuit delivering differential signals in the differential transmission system, and following is an example thereof.
FIG. 2 shows a second conventional output circuit for LVDS interface as a typical differential transmission system, wherein similar constituent elements are designated by reference symbols similar to those used in FIG. 1. The output circuit comprises: a first output section 11 having transistors M11 and M12, terminal resistor RTT1, input terminal IN1 and output terminal OUT1, which are common to the first conventional output circuit; and a second output section 12 having constituent elements similar to those in the first output section 11. Specifically, the second output section 12 comprises PMOS transistor M21 having a source connected to positive potential source line VDD, a drain connected to output terminal OUT2 and a gate connected to input terminal IN2, NMOS transistor M22 having a drain connected to the drain of transistor M21, a gate connected to the gate of transistor M21, and a source connected to grounded potential source line VSS, terminal resistor RTT2 having a first terminal connected to output OUT2 and a second terminal connected to terminal source VTT.
The values for terminal resistors RTT1 and RTT2, and terminal power supply voltage VTT are generally specified in a standard, wherein RTT1 and RTT2 are set at about 45 to 65.OMEGA. and VTT is set at about 1.1V to 1.4V.
In operation, when H-level potential which is close to potential VDD of source line VDD is supplied to input terminal IN1, and at the same time, L-level potential which is close to potential VSS of source line VSS is supplied to input terminal IN2, transistors M12 and M21 are ON, transistors M11 and M22 are OFF. Thus, a current path is formed from source line VDD to terminal source VTT via transistor M21 and terminal resistor RTT2, and another current path is formed from terminal source VTT to source line VSS via terminal resistor RTT1 and transistor M12. Accordingly, output terminal OUT1 supplies an L-level signal and output terminal OUT2 supplies an H-level signal. H-level signal potential VOH and L-level signal potential VOL are given by the expressions (1) and (2) as mentioned before.
When L-level potential close to potential VSS of source line VSS is supplied to input terminal IN1, and at the same time, H-level potential which is close to potential VDD of source line VDD is supplied to input terminal IN2, transistors M11 and M22 are ON, transistors M12 and M21 are OFF. Thus, a current path is formed from source line VDD to terminal source VTT via transistor M11 and terminal resistor RTT1, and another current path is formed from terminal source VTT to source line VSS via terminal resistor RTT2 and transistor M22. Accordingly, output terminal OUT1 supplies a H-level signal and output terminal OUT2 supplies a L-level signal.
As mentioned above, the technique for generating H-level and L-level for the output signal potential in the second conventional output circuit of the differential output system is similar to the case of the first conventional output circuit of the single phase system. Thus, if the variables in the expressions (1) and (2) are the same for both the circuits, H-level signal VOH and L-level signal VOL are equal to the above-mentioned numerical values (3), (4) and (5). It is possible to obtain desired small amplitude signal in the second conventional output circuit, similarly to the first conventional output circuit, by selecting ON-resistances RONP of PMOS transistors M11 and M21 or RONN of NMOS transistors M12 and M22, which are controlled based on the size of transistor elements in the integrated circuit depending on the power source potentials VDD, VSS and VTT, and terminal resistors RTT1 and RTT2 specified in advance.
Although both the conventional output circuits have advantages as described above, there is a problem that the variation in the output signal amplitude is considerably large.
In addition, the following three factors cause variations in the ON-resistances RONP and RONN, based on which H-level voltage VOH and L-level voltage VOL of the output signal of the first conventional output circuit are controlled.
The first factor is the influence by variations in the fabrication process of the MOS transistors. The fabrication process involves variation factors which affect shape variations in the resistor elements which constitute the output circuit. For example, variations in ON-resistance of the MOS transistor range generally about .+-.10% to .+-.20% depending on the shape of the transistor.
The second factor is the influence by the ambient temperatures at which the electronic device equipped with the integrated circuit is used under various environments. The ON-resistance of the MOS transistor changes, especially with the change of the ambient temperature: for example, the variations generally range about .+-.8% to .+-.16% with respect to a temperature rage of 100.degree. C.
The third factor is the influence by the variations in the power source potential. The power source potential supplied from outside the integrated circuit changes due to the potential loss on the source line in addition to the potential change of the external power source itself. The ON-resistance of the MOS transistor changes with the change of the input voltage: for example, the variations generally range about .+-.10% to .+-.15% with respect to a power source potential change of .+-.10%.
Thus, the variations in the ON-resistance of the MOS transistor generally range about .+-.28% to 51% when taking into account all the three factors mentioned above. The variations caused by the three factors generate variations of H-level VOH, L-level VOL and signal amplitude as follows: EQU VOH=1.713V to 2.007V (6) EQU VOL=0.993V to 1.287V (7) EQU VOH-VOL=0.426V to 1.014V (8)
The variations in the signal amplitude VOH-VOL are 1.7 times greater than the case in which the signal amplitude is calculated from the ON-resistance of the MOS transistor when the three factors are not taken into account, namely 0.6V as shown in expression (3). Variations in the output signal amplitude, especially in the case of variations in the higher direction, reduce and cancel the advantages of the small amplitude transmission described before.
In summary, the first and the second conventional output circuits have a problem of large variations in the signal amplitude to be solved, which cause reduction in transmission speed, increase in power dissipation and increase in the noise during signal transmission.